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On the performance of compact thermal models of electronic chip packages in conjugate board level simulation

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3 Author(s)
DeVoe, J. ; Dept. of Aerosp. & Mech. Eng., Arizona Univ., Tucson, AZ, USA ; Ortega, A. ; Berhe, M.

This study seeks to introduce a true conjugate solution methodology for compact thermal models of electronic packages in board level simulations using a computational fluid dynamic (CFD)/computational heat transfer (CHT) approach. CTM models were created for a BGA and CPGA based on thermal response data obtained by applying a set of non-redundant boundary condition sets to a fully-detailed model of each package. For consistency, the data was generated using the computational fluid dynamics tool IcePak™ run in a non-conjugate mode. Smeared models of the JEDEC standard printed circuit board for each package were created within the conjugate environment. The conductivities of these boards were ranged between three orders of magnitude. The fully-detailed model of each package were evaluated on these boards and in an unmounted state. The air velocity was varied for each between 1.0, 2.5, and 5.0 [m/s]. The fully-detailed model was replaced with the derived CTM and tested under similar conditions. Secondary sources were also investigate on elongated PCBs. The location of the source on the board was varied between three locations upstream of the package. The resultant junction temperature prediction of each setup was then compared.

Published in:

Semiconductor Thermal Measurement and Management Symposium, 2003. Ninteenth Annual IEEE

Date of Conference:

11-13 March 2003

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