Referenced Items are not available for this document.
A reconfigurable multiplier design for low-power field programmable gate arrays (FPGAs) is presented. Power consumption reduction is achieved through varying the depth of pipeline of the multiplier. The multiplier incorporates a capability of configuring itself dynamically, thus, is suitable for FPGA type of design.
Published in:
Electronics Letters
(Volume:39
,
Issue:
7
)
Date of Publication: 3 April 2003
- Page(s):
- 606 - 608
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 7616722
- Digital Object Identifier :
- 10.1049/el:20030364
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 22 April 2003
- Issue Date :
- 3 April 2003
- Sponsored by :
- Institution of Engineering and Technology
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