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Reconfigurable embedded MAC core design for low-power coarse-grain FPGA

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2 Author(s)
Sangjin Hong ; Dept. of Electr. & Comput. Eng., State Univ. of New York, Stony Brook, NY, USA ; S. -S. Chin

A reconfigurable multiplier design for low-power field programmable gate arrays (FPGAs) is presented. Power consumption reduction is achieved through varying the depth of pipeline of the multiplier. The multiplier incorporates a capability of configuring itself dynamically, thus, is suitable for FPGA type of design.

Published in:

Electronics Letters  (Volume:39 ,  Issue: 7 )