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A simple and fast scheme for code compression for VLIW processors

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4 Author(s)
J. Prakash ; Dept. of Comput. Sci. & Autom., Indian Inst. of Sci., Bangalore, India ; C. Sandeep ; P. Shankar ; Y. N. Srikant

Summary form only given. A scheme for code compression that has a fast decompression algorithm, which can be implemented using simple hardware, is proposed. The effectiveness of the scheme on the TMS320C62x architecture that includes the overheads of a line address table (LAT) is evaluated and obtained compression rates ranging from 70% to 80%. Two schemes for decompression are proposed. The basic idea underlying the scheme is a simple clustering algorithm that partially maps a block of instructions into a set of clusters. The clustering algorithm is a greedy algorithm based on the frequency of occurrence of various instructions.

Published in:

Data Compression Conference, 2003. Proceedings. DCC 2003

Date of Conference:

25-27 March 2003