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A real time FFT chip set: architectural issues

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2 Author(s)
Ruetz, P.A. ; LSI Logic Corp., Milpitas, CA, USA ; Cai, M.M.

The tradeoffs involved in the design of a real-time 40-MHz fast Fourier transform (FFT) chip set are discussed. Tradeoffs involving the algorithmic organization, device partitioning, the data format, and device architecture are examined. The chip set can compute FFTs with up to 2048 points at 40-MHz data rates (or 80-MHz data rates for real data) by using up to 20 chips or at 3-MHz rates when using only three devices. The 1.5-μ CMOS chip set has been designed, fabricated, and tested and is fully functional

Published in:

Pattern Recognition, 1990. Proceedings., 10th International Conference on  (Volume:ii )

Date of Conference:

16-21 Jun 1990