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A nondestructive quality evaluation and control procedure for large-area, -cut PZN-8%PT wafers is described. The crystals were grown by the flux technique engineered to promote  layer growth of the crystals. The wafers were sliced parallel to the  layer growth plane. Curie temperature (T/sub c/) variations, measured with matching arrays of dot electrodes (of 5.0 mm in center-to-center spacing), were found to be better than /spl plusmn/4.01/spl deg/C both within wafers and from wafer to wafer. After selective dicing to give final wafers of narrower T/sub c/ distributions (e.g., /spl plusmn/ 3.0/spl deg/C or better), the wafers were coated with complete electrodes and poled at room temperature at 0.7-0.9 kV/mm. Typical overall properties of the poled wafers were: K/sub 3//sup T/ = 5, 200 (/spl plusmn/10% from wafer to wafer), tan /spl delta/ < 0.01 (all wafers), and k/sub t/ = 0.55 (/spl plusmn/5%) (all percentage variations are in relative percentages). Then, the distributions of K/sub 3//sup S/, tan /spl delta/, and k/sub t/ were measured by the array dot electrode technique. The variations in K/sub 3//sup S/ (hence K/sub 3//sup T/) and k/sub t/ within individual wafers were found to be within 10% and 5%, respectively. The dielectric loss values, measured at 1 kHz, were consistently low, being <0.01 throughout the wafers. The k/sub t/ values determined by the dot electrodes were found to be about 5% smaller than those obtained with the complete electrodes, which can be attributed to an increase in capacitance ratio due to the partial electroding. The k/sub 33/ values, deduced using the relation K/sub 3//sup S/ /spl ap/ (1 k/sub 33//sup 2/) K/sub 3//sup T/, from the mean K/sub 3//sup S/ and overall K/sub 3//sup T/ values, average 0.94 (/spl plusmn/2%). The present work shows that the distribution of T/sub c/ within wafers can be used as a convenient check for the uniformity in composition and electromechanical properties of PZN-8%PT single crystal wafe- - rs. Our results show that, to control /spl Delta/K/sub 3//sup T/ and /spl Delta/k/sub t/ within individual wafer to /spl les/ 10% and 5%, respectively, the variation in T/sub c/ within the wafer should be kept within /spl plusmn/3.0/spl deg/C or better.