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Generic SoC QR array processor for adaptive beamforming

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4 Author(s)
Zhaohui Liu ; Sch. of Electr. & Electron. Eng., Queen's Univ. of Belfast, Ireland ; J. V. McCanny ; G. Lightbody ; R. Walke

A generic architecture for implementing a QR array processor in silicon is presented. This improves on previous research by considerably simplifying the derivation of timing schedules for a QR system implemented as a folded linear array, where account has to be taken of processor cell latency and timing at the detailed circuit level. The architecture and scheduling derived have been used to create a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition. This is demonstrated through the design of a single-chip architecture for implementing an adaptive beamformer for radar applications.

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IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing  (Volume:50 ,  Issue: 4 )