Optimal linearity testing of analog-to-digital converters using a linear model

To maintain an acceptable level of quality in the production of analog-to-digital converters (ADCs), the linearity metrics of every ADC has to be measured and checked against performance specification limits. As ADCs continue to improve in resolution, their testing has becoming increasingly demanding in terms of test time. In this paper, we demonstrate a technique for reducing the test time for ADCs. The technique is shown to be significantly better than currently available techniques and can be easily integrated into current production test methodologies. Experimental results in simulation and on actual hardware are shown to demonstrate the technique.