Skip to Main Content
Two approaches were demonstrated for fabricating microstructures after completion of CMOS circuits with aluminum metallization. The first approach employed n-type poly-Ge deposited at 400°C as a structural material with an SiO2 sacrificial layer and an HF release. The CMOS circuits were protected from the release etchant with an amorphous Si layer. Clamped-clamped lateral resonator test structures had quality factors in vacuum as high as ∼30000. Following a 500°C, 30 s RTA the poly-Ge stress was 200 MPa (tensile) and the resistivity was 5.3 mΩ-cm. In the second integration approach, p-type poly-Si0.35Ge0.65 deposited at 450°C was the structural material with poly-Ge as the sacrificial material and H2O2 as the release etchant. The H2O2 did not significantly etch the p-type poly-SiGe structural layer and no protection of the underlying CMOS layers was needed. For the first time, the fabrication of LPCVD surface microstructures directly on top of standard electronics was demonstrated, providing dramatic reductions in both MEMS-CMOS interconnect parasitics and device area. A folded flexure lateral resonator had a quality factor in vacuum as high as ∼15000. No stress or dopant-activation anneal was needed, since the in situ boron-doped poly-SiGe was found to have an as-deposited stress of only -10 MPa (compressive) and a resistivity of only 1.8 mΩ-cm.