By Topic

Phase noise contribution of the phase/frequency detector in a digital PLL frequency synthesiser

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Thompson, I. ; Nokia Telecommun. Ltd., Camberley, UK ; Brennan, P.V.

A theoretical basis for the figure of merit method used to quantify the phase noise plateau of a PLL frequency synthesiser is described. Analyses are developed both to calculate the in-band phase noise of a given synthesiser architecture and to predict the figure of merit from the phase/frequency detector parameters. A range of experimental results is provided to validate the theory.

Published in:

Circuits, Devices and Systems, IEE Proceedings -  (Volume:150 ,  Issue: 1 )