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A CV technique for measuring thin SOI film thickness

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5 Author(s)
Jian Chen ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Solomon, R. ; Chan, T.-Y. ; Ko, P.-K.
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A technique is developed to measure silicon-on-insulator (SOI) silicon device film thickness using a MOSFET. The method is based on CV measurements between gate and source/drain at two different back-gate voltages. The SOI devices used in this study were n/sup +/ polysilicon gate n-channel MOSFETs fabricated with modified submicrometer CMOS technology on SIMOX (separation by implanted oxygen) wafers. The SIMOX wafers were implanted with a high dose of oxygen ions (10/sup 18/ cm/sup -2/) at 200 keV and subsequently annealed at 1230 degrees C. The NMOS threshold boron implant dose is 2*10/sup 12/ cm/sup -2/. This method is simple, nondestructive, and no special test structure is needed. Using this technique, SOI film thickness mapping was made on a finished wafer and a thickness variation of +or-150 AA was found.<>

Published in:

Electron Device Letters, IEEE  (Volume:12 ,  Issue: 8 )