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In this paper, we describe skewed static logic (S/sup 2/L) with topology-dependent dual Vt which exhibits an energy-efficient operation. S/sup 2/L consumes less dynamic and static power compared to monotonic static (MS) CMOS. Speed degradation of S/sup 2/L, if any, can be offset by an accelerator circuit. We have designed NAND-NOR gate chains using 0.18-/spl mu/m CMOS technology and verified that S/sup 2/L reduces energy-delay product over MS CMOS by 27%-50%. We have also designed 32-b carry-lookahead adders and verified that S/sup 2/L with dual Vt reduces delay by 43% and energy-delay product by 31% for 1-V power supply over conventional CMOS circuit. Synthesis algorithm for S/sup 2/L is developed and the experimental results show S/sup 2/L consumes 23% less power than MS CMOS with minor increase in delay.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:11 , Issue: 1 )
Date of Publication: Feb. 2003