By Topic

Adaptive delay estimation for partitioning-driven PLD placement

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
M. Hutton ; Altera Corp., San Jose, CA, USA ; K. Adibsamii ; A. Leaver

This paper describes the application of weighted partitioning techniques to timing-driven placement on a hierarchical programmable logic device. We discuss the nature of placement on these architectures, the details of applying weighted techniques specifically to the programmable logic device (PLD) CAD flow, and introduce the new concept of adaptive delay estimation using phase local to increase performance. Empirical results show that these techniques, in a fully complete system with large industrial designs, give an average 38.5% improvement over the unimproved partitioning-based placement tool. Approximately two-thirds of this benefit is due to our improvements over a straightforward weighted partitioning approach.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:11 ,  Issue: 1 )