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Wiring requirement and three-dimensional integration technology for field programmable gate arrays

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4 Author(s)
Rahman, Arifur ; Polytech. Univ., Brooklyn, NY, USA ; Das, S. ; Chandrakasan, A.P. ; Reif, Rafael

In this paper, analytical models for predicting interconnect requirements in field-programmable gate arrays (FPGAs) are presented, and opportunities for three-dimensional (3-D) implementation of FPGAs are examined. The analytical models for two-dimensional FPGAs are calibrated by routing and placement experiments with benchmark circuits and extended to 3-D FPGAs. Based on system-level modeling, we find that in FPGAs with more than 20 K four-input look-up tables, the reduction in channel width, interconnect delay and power dissipation can be over 50% by 3-D implementation.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:11 ,  Issue: 1 )