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As interconnection delay plays an important role in determining circuit performance in field programmable gate arrays (FPGAs), timing-driven FPGA routing has received much attention recently. In this paper, we present a new timing-driven routing algorithm for FPGAs. The algorithm minimizes critical path delay for a given placed circuit using the Lagrangian relaxation technique. Lagrangian multipliers used to relax timing constraints are updated by subgradient method over iterations. Incorporated into the cost function, these multipliers guide the router to construct a routing tree for each net. During routing, the congestion constraints on each routing resource are also handled to route circuits successfully. Experimental results on benchmark circuits show that our approach outperforms the state-of-the-art versatile place and route router.