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Post-layout is an important stage in the modern very large scale integration (VLSI) design. In this stage, the extraction and verification tools can get the most accurate results with the complete layout information, and the layout problems can be detected precisely for further design improvements or optimizations. But the problem is that the design optimization is very hard to perform in post-layout. Every design modification is under tight geometry constraints. Usually the designer either changes layout manually by layout editor, or goes back to previous placement or routing stage in order to have the preferred results. How to modify the layout becomes a bottleneck in the post-layout optimization. In this paper, we propose a new method to resolve this problem called the triangulation encoding graph (TEG) method. Based on an improved topological layout representation and a set of layout operation algorithms, TEG provides an incremental layout modification environment for post-layout optimizations. Experimental results show that TEG is efficient and effective in processing industry VLSI designs.