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On integrating power and signal routing for shield count minimization in congested regions

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2 Author(s)
P. Saxena ; Strategic Comput.-Aided Design Labs., Intel Corp., Hillsboro, OR, USA ; S. Gupta

With worsening crosstalk in nanometer designs, it is increasingly important to control the switching cross-coupling experienced by critical wires. This is commonly done by inserting shields adjacent to these wires. However, the number of shielded wires can become extremely large, resulting in a large area impact. We address this problem at both the methodological and algorithmic levels, integrating the traditionally separate steps of power and signal routing in a safe manner to minimize the number of shields required to satisfy all shielding constraints. We propose a new abstraction for the block-level global and detailed routing hierarchy that allows accurate early estimation of crosstalk. Furthermore, we postpone the power routing in middle metal layers to after critical signal nets and their shields have been laid out (with maximal shield sharing), and then try to construct a fine-grained power grid out of the already routed shields. Given a routing on a metal layer, our adaptive power routing algorithm adds provably fewest new power lines to complete the power grid on that layer while guaranteeing adequate power delivery. Our approach has proven effective while designing some high-frequency blocks of a commercial gigahertz range microprocessor using a 0.18-μm process technology.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:22 ,  Issue: 4 )