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An effective congestion-driven placement framework

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2 Author(s)
U. Brenner ; Res. Inst. for Discrete Math., Univ. of Bonn, Germany ; A. Rohe

We present a fast but reliable way to detect routing criticalities in very large scale integration chips. In addition, we show how this congestion estimation can be incorporated into a partitioning based placement algorithm. Different to previous approaches, we do not rerun parts of the placement algorithm or apply a postplacement optimization, but we use our congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm. Computational experiments on chips with up to 1300000 cells are presented. The framework reduces the usage of the most critical routing edges by 9.0% on average, the running time increase for the placement is about 8.7%. However, due to the smaller congestion, the running time of routing tools can be decreased drastically, so the total time for placement and (global) routing is decreased by 47% on average.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:22 ,  Issue: 4 )