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In a memory, most power is dissipated in high-capacitive lines such as predecoder lines, wordlines, and bitlines. To reduce the power dissipation in these high-capacitive lines, this paper proposes three techniques using charge recycling and charge sharing. The first is the charge recycling predecoder (CRPD), the second is the charge recycling wordline decoder (CRWD), and the last one is the charge sharing bitline (CSBL) for a ROM. The CRPD and the CRWD recycle the previously used charge in predecoder lines and wordlines. Theoretically, the power consumption in predecoder lines and wordlines are reduced to a half. The CSBL reduces the swing voltage in the ROM bitlines to very small voltage using a charge sharing technique with three small capacitors. The CSBL can significantly reduce the power dissipation in ROM bitlines. The CRPD, the CRWD, and the CSBL consume 82%, 72%, and 64%, respectively, of the power of previous ROM designs. A charge recycling and charge sharing ROM (CRCS-ROM) with the CRPD, the CRWD, and the CSBL is implemented. A CRCS-ROM with 8K × 16 bits was fabricated in a 0.35-μm CMOS process. The CRCS-ROM consumes 8.63 mW at 100 MHz with 3.3 V. The chip core area is 0.51 mm2.