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A novel timing-driven placement using genetic algorithm

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4 Author(s)
Yoshikawa, M. ; VLSI Center, Ritsumeikan Univ., Shiga, Japan ; Terai, H. ; Fujita, T. ; Yamauchi, H.

This paper discusses a novel timing driven placement technique using Genetic Algorithms (GAs), and focuses particularly on the following points: (1) The algorithm has two-level hierarchical structure consisting of outline placement, which partitions a chip area into several areas, and detail placement, which determines cell positions in the partitioned area. The procedure for determining optimal cell positions is then explained. (2) For selection control, which is one of the genetic operations, new multi-objective functions are introduced at each phase for improving delay, reducing congestion and dispersing power. Results show improvement of 14.2% for the worst path delay on average.

Published in:

Mixed-Signal Design, 2003. Southwest Symposium on

Date of Conference:

23-25 Feb. 2003