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In this paper several methods to use eDRAM (embedded DRAM, on-chip DRAM) In packet switches are analyzed. A practical method using eDRAM as an output queue Is proposed especially in a shared bus packet switch. In the newly proposed output buffer architecture, hierarchical output buffer (HOB), of SRAM plays a role of the small FIFO buffer between a high-speed shared bus and a large eDRAM output buffer. The high density of eDRAM can provide larger capacity than static memories, which results in lower packet loss probability. This paper shows the performance analysis on the proposed HOB switch with the target port speed as 10Gbps for 10 Gigabit Ethernet or OC-192 standards.