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As the chip clock rate keeps increasing, the electrical performance of wire bond and bump connections which are using in advanced packaging is becoming the important consideration while choosing the package solution for high-speed devices. In this paper, the electrical performance of wire bond technology and bump with RDL (redistribution layer) technology is presented. By using full-wave 3D electromagnetic simulators, the experimental results, including the passive parasitic parameter analysis (AC resistance, inductance and capacitance) and scattering parameter analysis are presented. Discussions on the rise time, cross talk noise, and propagation delay for a 10 Gbit/s signal are also included.