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Compilation for FPGA-based reconfigurable hardware

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2 Author(s)
Cardoso, J.M.P. ; Fac. of Sci. & Technol., Univ. of Algarve, Faro, Portugal ; Neto, H.C.

This paper provides techniques for compiling software programs into reconfigurable hardware which offer faster and more efficient performance than the complex resource-sharing approaches typical of high-level synthesis systems. The Java-based compiler presented in this paper uses intermediate graph representations to embody parallelism at various levels.

Published in:

Design & Test of Computers, IEEE  (Volume:20 ,  Issue: 2 )