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A design-for-verification technique for functional pattern reduction

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3 Author(s)
Liu, C.-N.J. ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; I-Ling Chen ; Jing-Yang Jou

This technique reduces the number of required functional patterns by first defining conditions for hard-to-control (HTC) code in a hardware-description-language design and then using an algorithm to detect such code automatically. A second algorithm eliminates these HTC points by selecting a minimum number of nodes for control point insertion.

Published in:

Design & Test of Computers, IEEE  (Volume:20 ,  Issue: 2 )