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Fast fault simulation for nonlinear analog circuits

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2 Author(s)
Engin, N. ; Philips Res. Labs., Eindhoven, Netherlands ; Kerkhoff, H.G.

A new method of transient fault simulation uses dc bias grouping of faulty circuits and decreases the number of Newton-Raphson iterations needed to reach a solution. An experimental tool implementing this method achieves a speedup of 20% to 30% on a flat netlist.

Published in:

Design & Test of Computers, IEEE  (Volume:20 ,  Issue: 2 )