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Minimizing pattern count for interconnect test under a ground bounce constraint

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4 Author(s)
Marinissen, E.J. ; Philips Res. Labs., Eindhoven, Netherlands ; Vermeulen, B. ; Hollmann, H. ; Bennetts, R.G.

When testing the interconnect structures on a board, test programmers sometimes ask, How can I control the test pattern generation process to avoid ground bounce problems during Extest mode? Those wishing to satisfy a simultaneously-switching-outputs constraint will find several new solutions in this article.

Published in:

Design & Test of Computers, IEEE  (Volume:20 ,  Issue: 2 )