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A new approach to generate test sets for multiple faults of digital circuits is presented in the paper, which employs neural networks and simulated annealing technique. The neural network models for circuit are built, the test vectors of multiple faults in the circuit can be produced by computing the minimum energy states of the neural networks. An algorithm based on simulated annealing is proposed to compute the minimum states of energy functions, the algorithm has global convergence and has polynomial complexity under a decrement scheme of temperature. Experimental results shows that it is possible to obtain high fault coverage for testable multiple faults with the proposed approach without fault simulation.
Date of Conference: 17-19 Aug. 2002