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In this paper, a unified method for steady-state analysis of hard-switching and soft-switching DC-to-DC converters is presented. The power stage and the feedback control circuit forming the regulator are modeled separately and analyzed as two interconnected blocks. The intersection of the open loop DC steady-state characteristics of these cascaded blocks provides the initial condition for a guess candidate steady-state solution (CS). The CS is validated as true steady-state solution (TS) if the bias conditions of switching devices are fulfilled everywhere in the switching period, otherwise the CS is changed according to the conditions violated. The CS approaches the TS through an iterative process of validation. The basic tools adopted to ensure a reliable computation of the CS are interval analysis (IA), for the identification of the commutation instants (CI), and the compensation theorem (CT), for the analysis of commutations. Some examples of applications to hard-switching and soft-switching DC-DC regulators are presented.