By Topic

A parallel algorithm for power estimation at gate level

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Nourani, M. ; Center for Integrated Circuits & Syst., Texas Univ., Richardson, TX, USA ; Nazarian, S. ; Afzali-Kusha, A.

In this paper we present an analytical method for estimating switching probability and power consumption of combinational circuits at the gate level. Considering the signal correlation and multiple-bit input switching, we propose an efficient scheme to estimate switching probability and dynamic power consumption of combinational CMOS circuits at the gate level accurately. Additionally, our algorithm has potential not to propagate the estimated values through the circuit and thus can be run in parallel machines for very large circuits.

Published in:

Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on  (Volume:1 )

Date of Conference:

4-7 Aug. 2002