By Topic

A new ternary MVL based completion detection method for the design of self-timed circuits using dynamic CMOS logic

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Connell, C.L. ; Center for Integrated Circuits & Syst., Texas Univ., Richardson, TX, USA ; Balsara, P.T.

The performance and success of many self-timed design methodologies commonly rely heavily on completion detection schemes in order to reliably acknowledge the termination of a computation associated with a self-timed functional block. A particularly vexing problem associated with many self-timed completion detection schemes proposed in the literature, is the task of implementing the robust and successful generation of a completion done signal, denoting the termination of a self-timed event, on every computation handled by a self-timed functional block. Many research groups who have focused on the development of asynchronous self-timed design methodologies have proposed methods to successfully detect the completion of a self-timed computation. However, a universally acceptable solution that successfully detects the completion of a self-timed event on every cycle of computation for an arbitrary self-timed functional block, remains to this day, an elusive technical issue. A specific case, related to data conditioning, that proves to be fundamentally problematic in many self-timed completion detection schemes that have been proposed, involves the successful generation of a selftimed components' completion detection signal on consecutive cycles of computation. This is equivalent to cases where the nature of the input data is such that the resulting output generated on subsequent computational cycles is the same as the previous cycles' result ("same state similarity"). In this paper, the authors' propose a novel approach to completion detection, for use in asynchronous self-timed designs, that employs a ternary multiple valued logic ("MVL") approach using dynamic CMOS circuit design techniques, that guarantees the fail-proof generation of event termination on every self-timed computational cycle, including cases of same state similarity.

Published in:

Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on  (Volume:1 )

Date of Conference:

4-7 Aug. 2002