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Modeling and verification of a pipelined CPU

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1 Author(s)
L. Ivanov ; Dept. of Comput. Sci., Iona Coll., New Rochelle, NY, USA

In this paper, we present a formal model of a pipelined version of the DLX processor, and verify the correct operation of the pipeline using a formal verification approach based series-parallel posets. We illustrate how the method can be used to detect pipeline hazards and other problems. The full verification was carried out automatically with the help of a verification tool, based on algorithms with low time- and space complexity.

Published in:

Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on  (Volume:3 )

Date of Conference:

4-7 Aug. 2002