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A 0.58-1 Gb/s CMOS data recovery circuit using a synchronous digital phase aligner

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2 Author(s)
Cheung, T.S. ; Dept. of Network Core Technol., ETRI, Daejon, South Korea ; Lee, B.C.

A data recovery circuit using a newly proposed synchronous digital phase aligner is realized for multi-link applications. The proposed circuit is implemented with 0.35 μm CMOS process technology. The experimental results show that the proposed circuit successfully recovers incoming 0.58-1 Gb/s of 231-1 pseudo random bit sequence with less than 10-14 of bit error rate.

Published in:

Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on  (Volume:3 )

Date of Conference:

4-7 Aug. 2002