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In this paper a novel architecture for a scalable DSP core is proposed. Due to the increase of system resources available on last generation FPGA, the System-on-Chip paradigm can be borrowed from classical silicon implementations into reconfigurable environments. Presently, off-the-shelf devices suffer the need for remarkable static power consumption: however it is forecastable that technology improvements will extend FPGA usage to mobile systems. Despite the increasing importance gathered by reconfigurable computing, a lack of retargetable soft-processor IP is felt. In particular, this IP aims to fill the existing gap between specific coprocessor units and general purpose soft cores. The proposed architecture exhibits interesting figures both in terms of area occupation as well as maximum operative clock frequency. In order to validate the system performance, some common telecommunication algorithms have been mapped on the DSP. Good experimental results have been obtained running at 89 MHz on a XILINX XCV1000.