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This paper reports a low-power VLSI design of a HMM based speech recognition system. Output probability calculation is the most computationally expensive part of continuous HMM (CHMM) based speech recognition. The proposed architecture calculates the output probability with parallel and pipeline processing. It enables to reduce memory access and have high computing efficiency. The novel point is the efficient use of register arrays that reduce memory access considerably compared with any conventional method. The implemented system can achieve a real time response with lower clock in a middle size vocabulary recognition task (100-1000 words) by using this technique.