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Novel low CTE-high stiffness organic and inorganic boards were evaluated for flip-chip on board technology without underfill. Standard liquid-liquid thermal shock tests were carried out on test vehicles with different board materials and failure modes were characterized. In-situ warpage and stress measurements were made to analyze the observed failure modes and to set guidelines for optimal board material selection. The effect of interlayer dielectric thickness on the package reliability has also been studied. The reliability test results are in accordance with the inferences from the in-situ warpage and stress measurements and it can be concluded that along with low CTE, high modulus is an inevitable substrate property requirement for flip-chip reliability without underfill in next-generation packages. This paper also presents photostimulated luminescence spectroscopy as a nondestructive and direct technique for the in-situ stress measurement in microsystems and thus a powerful means for reliability assessment.
Electronics Packaging Technology Conference, 2002. 4th
Date of Conference: 10-12 Dec. 2002