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This paper presents an efficient design methodology to develop IP-core functions in VHDL for control systems. This methodology is able to cope with different optimization constraints such as the reduction of both the development time and the execution time and the minimization of the consumed resources of the chip. Our approach uses the AAA methodology (algorithm architecture adequation), which allows to rapidly develop and optimize the implantation of the DFG (data flow graph) of an algorithm. In order to illustrate the efficiency of this methodology, the authors present the implantation of an antiwindup PI controller on a single field programmable gate array (FPGA) applied to the control of a DC/DC converter.
IECON 02 [Industrial Electronics Society, IEEE 2002 28th Annual Conference of the] (Volume:3 )
Date of Conference: 5-8 Nov. 2002