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Summary form only given. We look at how, as designers of communications systems on silicon, we have to deal with new wireless systems driven by three fast changing parameters - the exploding algorithmic complexity in new wireless systems, the semiconductor industry marching to Moore's Law, and the increasing gap between the raw computational complexity required and the realizable computational power offered by traditional computer architectures used in wireless communications. With new 3G and WLAN applications requiring more than a tenfold increase in DSP horsepower per subscriber, the challenge of delivering communication platforms for both wireless infrastructure and terminals is formidable. We begin by examining the gap we call "Shannon vs. Moore", - how the complexity in parameter estimation and sequence detection algorithms required in new wireless applications is growing exponentially, at a pace faster than the growth of digital signal processor performance. We examine how battles are being fought in the world of instruction-set processors, programmable logic, and ASICs to address this complexity. We close by showing that there is a spectrum of techniques to optimally match algorithms and architectures that offers compelling price/performance solutions, all within the bounds of today's plain-vanilla digital CMOS technology.