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An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-μm CMOS

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4 Author(s)
Stonick, J.T. ; Accelerant Networks Inc., Beaverton, OR, USA ; Gu-Yeon Wei ; Sonntag, J.L. ; Weinlader, D.K.

This paper describes a backplane transceiver, which uses pulse amplitude modulated four-level (PAM-4) signaling and continuously adaptive transmit-based equalization to move 2.5-GBd/s symbols totalling 5 Gb/s across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors. The 17-mm2 device is implemented in a 0.25-μm CMOS process, operates off of 2.5- and 3.3-V supply voltages, and consumes 1 W.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:38 ,  Issue: 3 )

Date of Publication:

Mar 2003

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