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Caches and hash trees for efficient memory integrity verification

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5 Author(s)
B. Gassend ; Lab. for Comput. Sci., MIT, Cambridge, MA, USA ; G. E. Suh ; D. Clarke ; M. van Dijk
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We study the hardware cost of implementing hash-tree based verification of untrusted external memory by a high performance processor. This verification could enable applications such as certified program execution. A number of schemes are presented with different levels of integration between the on-processor L2 cache and the hash-tree machinery. Simulations show that for the best of our methods, the performance overhead is less than 25%, a significant decrease from the 10× overhead of a naive implementation.

Published in:

High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. The Ninth International Symposium on

Date of Conference:

8-12 Feb. 2003