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Dynamic voltage scaling with links for power optimization of interconnection networks

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3 Author(s)
Li Shang ; Dept. of Electr. Eng., Princeton Univ., NJ, USA ; Li-Shiuan Peh ; N. K. Jha

Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these networks get deployed in a wide range of new applications, where power is becoming a key design constraint, we need to seriously consider power efficiency in designing interconnection networks. As the demand for network bandwidth increases, communication links, already a significant consumer of power now, will take up an ever larger portion of total system power budget. In this paper we motivate the use of dynamic voltage scaling (DVS) for links, where the frequency and voltage of links are dynamically adjusted to minimize power consumption. We propose a history-based DVS policy that judiciously adjusts link frequencies and voltages based on past utilization. Our approach realizes up to 6.3× power savings (4.6× on average). This is accompanied by a moderate impact on performance (15.2% increase in average latency before network saturation and 2.5% reduction in throughput.) To the best of our knowledge, this is the first study that targets dynamic power optimization of interconnection networks.

Published in:

High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. The Ninth International Symposium on

Date of Conference:

8-12 Feb. 2003