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Systolic array implementation of block based Hopfield neural network for pattern association

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3 Author(s)
Ming-Jung Seow ; Dept. of Electr. & Comput. Eng., Old Dominion Univ., Norfolk, VA, USA ; Hau Ngo ; Asari, V.

This paper suggests a systolic array implementation of block based Hopfield neural network architecture using completely digital circuits. The design is based on rewriting the energy equation of the Hopfield neural network to a systolic (or modular) form. The performance of the proposed architecture is evaluated by applying various binary inputs and it is observed that the network provides massive parallelism and can be extended by cascading identical chips.

Published in:

VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on

Date of Conference:

20-21 Feb. 2003