Architecture, memory and interface technology integration of an industrial/ academic configurable system-on-chip (CSoC)

This paper describes the actual status and results of a dynamically configurable system-on-chip (CSoC) integration, consisting of a SPAR C-compatible LEON processor-core, a commercial coarse-grain XPP-array of suitable size from PACT XPP Technologies AG, and application-tailored global/local memory topology with efficient Amba-based communication interfaces. The given adaptive architecture is synthesized within an industrial/academic SoC project onto 0.18 and 0.13 μm UMC CMOS technologies at Universitaet Karlsruhe (TH). Due to exponentially increasing CMOS mask costs, essential aspects for the industry are now adaptivity of SoCs, which can be realized by integrating reconfigurable re-usable hardware parts on different granularities into configurable systems-on-chip (CSoCs).