Novel circuit styles for minimization of floating body effects in scaled PD-SOI CMOS

SOI (silicon-on-insulator) technology suffers from a number of floating body effects, most notably parasitic bipolar and history effects. These are influenced by the rapidly increasing gate tunneling current caused by an ultra-thin gate oxide, even at scaled V/sub DD/s. This paper analyzes these effects in detail and proposes a number of novel circuit styles to minimize them. Simulation results are based on model parameters from an AMD 0.25 /spl mu/m PD-SOI process.