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Novel circuit styles for minimization of floating body effects in scaled PD-SOI CMOS

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2 Author(s)
Das, K.K. ; Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA ; Brown, R.B.

SOI (silicon-on-insulator) technology suffers from a number of floating body effects, most notably parasitic bipolar and history effects. These are influenced by the rapidly increasing gate tunneling current caused by an ultra-thin gate oxide, even at scaled VDDs. This paper analyzes these effects in detail and proposes a number of novel circuit styles to minimize them. Simulation results are based on model parameters from an AMD 0.25 μm PD-SOI process.

Published in:

VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on

Date of Conference:

20-21 Feb. 2003