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Three-dimensional integration technologies have been proposed in order to mitigate design challenges posed by deep-submicron interconnect. By providing multiple layers of active devices together with high-density local interconnects between these layers, 3-D technologies give digital-circuit designers greater freedom in meeting power and delay budgets that are increasingly interconnect-dominated. In this paper, we quantify the benefits 3-D integration can provide, using specific circuit benchmarks. We perform this analysis using a suite of circuit design tools we have developed for 3-D integration. We observe that on average, 28% to 51% reduction in total wire length is possible over two to five wafers respectively; similarly, 31% to 56% reduction in the length of the longest wire is achievable. We also characterize the impact of technology parameters on these reductions.