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The architecture of high-speed matched filter for searching synchronization in DSSS receiver

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1 Author(s)

A high-speed matched filter for searching synchronization in direct sequence spread spectrum (DSSS) receiver is studied. A model to implement the matched filter by hardware description languages (HDL) is proposed. The proposed model is based on parallel processing and pipeline architecture including circular buffer, multiplier, adder, and code look-up table. The proposed model is analyzed with respect to the performance and compared with a conventional digital signal processor (DSP) implementation.

Published in:

Communication Systems, 2002. ICCS 2002. The 8th International Conference on  (Volume:2 )

Date of Conference:

25-28 Nov. 2002

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