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Design and implementation of HDTV encoder system with parallel processing architecture

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3 Author(s)
Hongkai Xiong ; Inst. of Image Commun. & Inf. Process., Shanghai Jiao Tong Univ., China ; Songyu Yu ; Wei Ye

This paper presents a design procedure for an HDTV encoder with parallel processing architecture, which could get out the dilemma lying in high-speed digital processing circuitry and real-time compression. In the proposed system, an original HDTV picture is split to multiple sub-pictures of MPEG-2 MP@ML level, and then multiple sub-picture encoding modules (SEM) perform, respectively and simultaneously, MPEG-2 coding in the light of a joint rate control scheme. A normative HDTV PES stream of MPEG-2 MP@HL is built up by compositing multiple ES streams with different bit-rate. The paper hits the high points and supply appropriate implementation strategy during the propose design framework.

Published in:

Communication Systems, 2002. ICCS 2002. The 8th International Conference on  (Volume:2 )

Date of Conference:

25-28 Nov. 2002

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