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Design of efficient system-on-chips (SoCs) requires thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardware in order to meet the cost as well as the performance constraints. However, faster time to market requires automation of synthesis of these code segments of the application from high level specification such as C along with its interfaces. Such a synthesis system should be able to generate hardware which is easily pluggable in various types of architectures, as well as augment the application code to automatically take advantage of this new hardware component. In this paper, we address this problem and present an approach for complete SoC synthesis. We automatically generate synthesizable VHDL for the compute intensive part of the application along with necessary interfaces. Our approach is generic in the sense that it supports various processors and buses by keeping a generic hardware interface on one end and a dedicated one on the other. The generated hardware can be used in a tightly or loosely coupled manner in terms of memory and register communication. We present the effectiveness of this approach for some commonly used image processing spatial filter applications.
Date of Conference: 4-8 Jan. 2003