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Efficient layout of code and data sections in various types/levels of memory in an embedded system is very critical not only for achieving real-time performance, but also for reducing its cost and power consumption. In this paper we formulate the optimal code and data section layout problem as an integer linear programming (ILP) problem. The proposed formulation can handle: (i) on-chip and off-chip memory, (ii) multiple on-chip memory banks, (iii) single and dual ported on-chip RAMS, (iv) overlay of data sections, and (v) swapping of code and data (from/to external memory). Our experiments demonstrate that, for a moderately complex embedded system, the optimal results produced by our formulation took only a few minutes on a PC, and it matches, in terms of performance and on-chip memory size, with a hand-optimized code/data layout which took 1 man-month.