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This paper discusses the NP-complete problem of reconfiguring a two-dimensional degradable VLSI/WSI array under the row and column routing constraints. A new strategy for row selection in the logical array is proposed and the earlier approach by Low et. al. is simplified. A flaw in Low's algorithm is also addressed. Experimental results show that our algorithm is approximately 50% faster than the most efficient algorithm, cited in the literature, without loss of performance.