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A run-time reconfiguration algorithm for VLSI arrays

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2 Author(s)
Wu Jigang ; Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore, Singapore ; S. Thambipillai

This paper discusses the NP-complete problem of reconfiguring a two-dimensional degradable VLSI/WSI array under the row and column routing constraints. A new strategy for row selection in the logical array is proposed and the earlier approach by Low et. al. is simplified. A flaw in Low's algorithm is also addressed. Experimental results show that our algorithm is approximately 50% faster than the most efficient algorithm, cited in the literature, without loss of performance.

Published in:

VLSI Design, 2003. Proceedings. 16th International Conference on

Date of Conference:

4-8 Jan. 2003