By Topic

A framework for energy and transient power reduction during behavioral synthesis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
S. P. Mohanty ; Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA ; N. Ranganathan

In deep submicron and nanometer designs for battery driven portable applications, the minimization of total energy, average power, peak power, and peak power differential are equally important. In this paper, we propose a framework for simultaneous reduction of these energy and transient power components during behavioral synthesis. A new parameter called "Cycle Power Profile Function" (CPF) is defined which captures the transient power characteristics as a weighted sum of mean cycle power and mean cycle differential power. Minimizing this parameter using multiple voltages and dynamic clocking results in reduction of both energy and transient power. Based on the above, a datapath scheduling algorithm called "CPF-Scheduler" is developed which attempts to minimize the CPF. Experimental results show that for two voltage levels, three operating frequencies, switching activity of 0.5 and power profiling factor of 0.5, the scheduler achieves (i) total energy reductions in the range of 27 - 53%, (ii) average power reductions in the range of 40 - 73% (iii) peak power reductions in the range of 58 - 78% and (iv) peak power differential reductions in the range of 60 - 97%. Further, the impact of switching, profiling factor and resource constraints on the power profile is studied in detail.

Published in:

VLSI Design, 2003. Proceedings. 16th International Conference on

Date of Conference:

4-8 Jan. 2003