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In this paper, single-rail and dual-rail mixed pass-transistor logic (PTL) and static CMOS circuits are presented. The circuits were synthesized using a genetic algorithm that determines the best mixture of PTL and static cells based on area and power. The mixed PTL/static circuits using the proposed method are compared with their static counterparts synthesized using a commercial logic synthesis tool in terms of area, delay and power in a 0.13 μm floating-body partially depleted silicon-on-insulator (SOI) and a 0.13 μm bulk CMOS technologies. Our experimental results on benchmark circuits from a commercial microprocessor indicates that the proposed mixed PTL/static circuits in both SOI and bulk CMOS technology outperforms their static counterparts in power consumption and/or performance.